Reconfigurable logic test methodologies for ISDN

  • Patrick Sugrue

    Student thesis: Master's Thesis


    This portfolio presents three separate design and development projects. Each project addresses a different aspect of ISDN testing. Field programmable gate array (FPGA) technology was employed to facilitate the development. The design and development work produced a hardware platform that could be reconfigured to provide the test features associated with each project. The three projects were, a power spectrum density (PSD) measurement facility for basic-rate ISDN, a bit-error rate test (BERT) facility for basic-rate ISDN, and a passive monitor for basic-rate ISDN. The project work demonstrated how greater test feature integration could be achieved while allowing future features to be easily incorporated as software upgrades reducing the development time to market for new products.
    Date of AwardDec 2003
    Original languageEnglish
    SupervisorJurgen Richter (Supervisor) & Ralf Patz (Supervisor)


    • ISDN testing
    • Field programmable gate array
    • FPGA
    • power spectrum density
    • PSD
    • Basic-Rate ISDN
    • bit-error rate test
    • BERT
    • Digital Subscriber Line
    • DSL
    • Integrated Systems Digital Network

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