Understanding Microbenchmark Detection of Existing Exploits in Apple M1 and M2 Chips

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Understanding the causes, effects, and detection / mitigation methods of side-channel attacks (SCAs) is essential in providing a secure environment. Current studies into SCAs have focused on Intel microarchitecture and Apple Silicon chips (such as M1 and M2) have been left under-represented in the research literature. The aim of this paper is to identify a gap in microarchitectural research of M1 and M2 Apple chips. The long-term objective of this research is to apply the Unified Side Channel Attack – Model (USCA-M) four-phase testing process to identify the critical components used within the exploit and at a low-level catch the Hardware Performance Counter (HPC) events of M1 and M2 chips.
Original languageEnglish
Title of host publication2024 12th International Symposium on Digital Forensics and Security (ISDFS)
PublisherInstitute of Electrical and Electronics Engineers
Number of pages4
ISBN (Electronic)979-8-3503-3036-6, 979-8-3503-3037-3
DOIs
Publication statusPublished - 29 Apr 2024
Event12th International Symposium on Digital Forensics and Security - Trinity University, San Antonio, United States
Duration: 29 Apr 202430 Apr 2024

Publication series

Name2024 12th International Symposium on Digital Forensics and Security (ISDFS)

Conference

Conference12th International Symposium on Digital Forensics and Security
Abbreviated titleISDFS 2024
Country/TerritoryUnited States
CitySan Antonio
Period29/04/2430/04/24

Keywords

  • microarchitecture exploits
  • side channel attacks
  • M1 chip
  • M2 chip

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