This paper provides a behavioral model of 28nm FDSOI technology for a wide temperature range. In this work, a multivariate interpolation lookup tables (LUTs) model considering temperature dependence for nanometer CMOS transistors is presented. The new approach is validated by comparison with the bias current and capacitances tables in a given wide range of the temperature for the simulation of MOS transistor circuits. This novel approach significantly enhances the simulation speed with sufficient accuracy via a dynamic programming procedure over the current state of the art models. Simulation results are implemented in a 28-nm fully depleted SOI (FDSOI) technology. The proposed model achieving speedups of up to eight orders of magnitude at transistor level considering temperature effect found in FDSOI compared to simulations with both the BSIM SOI model and the Lagrange interpolation lookup table model.