This paper presents novel architectures for efficient implementation of Discrete Orthogonal Transforms (DOTs) using an FPGA based parameterisable system. These transforms are important in many signal and image processing applications including image and speech compression, filtering and coding. Two novel architectures for DOTs using both systolic architecture and distributed arithmetic design methodologies are presented. The first approach uses the Modified Booth-encoder-Wallace trees Multiplication (MBWM) algorithm for a systolic architecture implementation. The second approach is based on both distributed arithmetic ROM and accumulator structure, and Offset Binary Coding technique (OBC). Implementations of the algorithms on a Xilinx FPGA board are described. Distributed arithmetic approach exhibits better performances when compared with the systolic architecture approach.
|Title of host publication
|Proceedings of 11th European Signal Processing Conference
|Published - 2002