Understanding Microbenchmark Detection of Existing Exploits in Apple M1 and M2 Chips

Allbwn ymchwil: Cyfraniad at gynhadleddPapuradolygiad gan gymheiriaid

Crynodeb

Understanding the causes, effects, and detection / mitigation methods of side-channel attacks (SCAs) is essential in providing a secure environment. Current studies into SCAs have focused on Intel microarchitecture and Apple Silicon chips (such as M1 and M2) have been left under-represented in the research literature. The aim of this paper is to identify a gap in microarchitectural research of M1 and M2 Apple chips. The long-term objective of this research is to apply the Unified Side Channel Attack – Model (USCA-M) four-phase testing process to identify the critical components used within the exploit and at a low-level catch the Hardware Performance Counter (HPC) events of M1 and M2 chips.
Iaith wreiddiolSaesneg
StatwsWedi’i dderbyn/Yn y wasg - 29 Chwef 2024
Digwyddiad12th International Symposium on Digital Forensics and Security - Trinity University, San Antonio, Yr Unol Daleithiau
Hyd: 29 Ebr 202430 Ebr 2024

Cynhadledd

Cynhadledd12th International Symposium on Digital Forensics and Security
Teitl crynoISDFS 2024
Gwlad/TiriogaethYr Unol Daleithiau
DinasSan Antonio
Cyfnod29/04/2430/04/24

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